01

Market Trend（Dec. 10）

South Korean government to invest US$3.1bn in a new wafer foundry

On December 10, the South Korean government announced that it plans to invest 4.5trn won (about US$3.1bn) to build 12-inch mature process (≥ 40nm) wafer foundry. The project will begin construction in 2026 and will be put into operation at the end of 2028. The project, led by the Ministry of Trade Industry and Resources (MOTIR), will be based in Cheongju, North Chungcheong Province, and will form “Manufacturing + Testing” facilities based on the existing packaging & testing cluster. The foundry will provide R&D, small-batch and special foundry services for fabless design firms, defense research institutes and SME, aiming to reduce the percentage of outsourced defense semiconductors from 99% to less than 60%, and a law will also be proposed to prioritize the procurement of domestic chips used for national security facilities. The government has also set up a “Special Council on Semiconductor” under the direct authority of the President to co-ordinate policy resources such as finance, taxation, land, and talents. South Korea plans to invest 700trn won to build 10 new wafer fabs by 2047 and increase the size of fabless industry by ten folds, thus creating a foundry-design synergistic ecology similar to that of TSMC.

Comments:This investment is seen as a key move of South Korea to consolidate the two wheel drive of storage + logic chips in the AI era, reduce reliance on mature overseas processes, strengthen supply chain security, and also add new regional variables to the landscape of global wafer foundry. The positioning of South Korea’s US$3.1bn 40nm mature process fabs: The fabs can not only avoid fiercely competing with TSMC and Samsung in 3nm process but also makes use of local idle old production lines, which reduce the depreciation cost by 30%, to realize “national defense confidentiality + rapid Iteration”. They hope to attract European and American fabless business to take South Korea as their “second source”. If the plan of 10 fabs is implemented, South Korea will have the three identities of foundry of storage chips, high-end logic chips, and mature process foundry. The global semiconductor landscape may present a “US-South Korea-Taiwan” triple-pole form. For Chinese mainland, this means that the competition in mature processes will be upgraded from “price war” to “security story”, and Chinese mainland should speed up alternative certification and distinctive process differentiation to secure its share in a new round of capacity expansion.

02

Company Trend（Dec. 11）

EU approves two new chip fabs in Germany

On December 10, the South Korean government announced that it plans to invest 4.5trn won (about US$3.1bn) to build 12-inch mature process (≥ 40nm) wafer foundry. The project will begin construction in 2026 and will be put into operation at the end of 2028. The project, led by the Ministry of Trade Industry and Resources (MOTIR), will be based in Cheongju, North Chungcheong Province, and will form “Manufacturing + Testing” facilities based on the existing packaging & testing cluster. The foundry will provide R&D, small-batch and special foundry services for fabless design firms, defense research institutes and SME, aiming to reduce the percentage of outsourced defense semiconductors from 99% to less than 60%, and a law will also be proposed to prioritize the procurement of domestic chips used for national security facilities. The government has also set up a “Special Council on Semiconductor” under the direct authority of the President to co-ordinate policy resources such as finance, taxation, land, and talents. South Korea plans to invest 700trn won to build 10 new wafer fabs by 2047 and increase the size of fabless industry by ten folds, thus creating a foundry-design synergistic ecology similar to that of TSMC.

Comments:EU said the investment is a key step in the implementation of the European Chip Act, which aims to complement the bottleneck of “weak manufacturing ability” despite of “strong design ability”, to strengthen the resilience of its supply chain and reduce dependence on external production capacity. At the same time, it drives the clustering of equipment, materials, packaging and other upstream and downstream industries, to help Europe to achieve its goal of accounting for 20% of global semiconductor production by 2030. EU used a large subsidy under the European Chip Act to “build two fabs in one city” in Germany, seemingly replicating the Asian model but in fact showing a differentiated strategy of “Automotive + Open Foundry”: The 28nm and larger vehicle-grade chips can directly dock with auto makers in Europe to shorten the lead time of scarce chips. The 14nm EUV platform provides small and medium-sized design companies with local advanced processes to reduce their dependence on American and Asian suppliers. The €600mn subsidy is used to leverage more than €3bn private investment, with a leverage ratio of about 1:5, which is in line with the EU fiscal discipline of “small subsidies for large capacity” .

03

Company Trend（Dec. 11）

Rivian unveils customized AI chips to replace Nvidia chips and enhance self-driving capabilities

On December 11, Rivian Automotive, an American pure electric pickup truck maker, unveiled its first custom computer chip Rivian Autonomy Processor 1(RAP1). The chip adopts TSMCs 5nm process and multi-chip packaging, has 1600 sparse INT8 TOPS and can process 5 billion pixels per second. Its memory bandwidth is 205 GB/s, and its performance is four times that of the current NVIDIA Orin platform, but the cost per truck is down hundreds of dollars. RAP1 will drive the 3rd-gen Autonomy Compute Module 3 to work with the new LIDAR and Large Driving Model. It will be first applied on R2 SUV in 2026 and the subscription service Autonomy+ will be launched at a one-time fee of US$2,500 or US$49.99 per month, half of that of Tesla FSD. According to Rivian CEO, the company’s self-developed chips will reduce external dependence, improve collaboration between hardware and software, and support multi-chip cascading extensions, thus laying a computing foundation for L4 functions such as point-to-point navigation, automatic lane change to be launched in 2027. Facing the slowdown in demand for electric cars in USA and competition from Chinese automakers, Rivian expects to use “AI-defined vehicle” to reshape auto technological tag to boost sales and capital market confidence.

Comments:Rivian abandoned Nvidia chips but self-developed RAP1. This means this North American ‌new energy vehicle startup removed Orin from its core AI chip options, and it has the same significance as Tesla’s FSD Chip has. Its 5nm process, 1600 TOPS, and a reduced price of several hundred dollars prove that it has successfully made a closed loop of “algorithm-chip-auto model”. More importantly, the subscription price is halved, which is directly aligning with Tesla FSD, aiming to use hardware cost reduction to exchange for software penetration, which is expected to improve cash flow by increasing its revenue of auto software from less than 3% to more than 10%. However, the risk is also very clear. If TSMCs 5nm capacity is occupied by Apple and Qualcomm, it is difficult for Rivian to have any priority; Since the self-developed chip needs to be iterated continuously, once the launch of L4 is delayed, the hardware will become sunk costs; If the US-China supply chain meets tariff fluctuations, the advantages of wafer and packaging costs will be backfired. For Chinese automakers, the case of Rivian chip suggests that self-developed AI chip is no longer a “flagship symbol” but a “cost weapon”.

04

Company Trend（Dec. 12）

TSMC to shift its Kumamoto Fab-2 to 4nm amid AI demand

In mid-December, TSMC has confirmed that it suspended the construction of JASM Fab-2 and is weighing shifting the fab to be put into operation in 2027 from 6nm/7nm to 4nm to respond to the urgent need of higher energy efficiency and density of AI chips. According to insiders, TSMC’s major customers, including Nvidia, Apple, and others, speed up migrating their chips to sub-4nm/5nm process nodes, resulting in the falling of the utilization rate of 6nm/7nm capacity, which makes TSMC reassess its technical configuration. If it decides to upgrade the fab, the fab needs to be equipped with EUV lithography machine and redesign the clean room and the pipeline. Although about 90% of the equipment can be reused, the mass production time node can still be delayed. The Japanese government regards this move as a key step to gain the most advanced logic processes, and has committed to subsidizing and matching talents. TSMC said it would introduce advanced packaging such as CoWoS to form an “FEOL + BEOL” one-stop capacity to address the supply and demand gap for AI GPUs. However, the plan has not yet been finalized, and the company simply stated that “ it is negotiating the details of the plan with customers and partners.”

Comments:TSMC’s plan of shifting Kumamoto Fab-2 from 6nm/7nm to 4nm is a precise move to “exchange capacity for track”. In the AI wave, the 6nm/7nm demand is quickly replaced by the demand for 5nm/4nm and smaller nodes. If the JASM fab starts production as originally planned, there is a risk that it will be idled immediately after starting operation; after the upgrade, the fab will provide advanced nodes based on EUV in Japan for the first time, securing Nvidia’s and Apples second overseas source of next-gen AI chips. At the same time, the CoWoS packaging will also be moved to Kumamoto to form an “FEOL + BEOL” one-stop capacity, significantly shortening the lead time of GPU. For Japan, it can get access to the most advanced logic processes in the country at one go, and the government subsidies are shifted from “giving large-scale funds” to “giving technology” to stimulate the upstream and downstream suppliers of the supply chain to flow back; For TSMC, it can make use of the dividends from the devaluation of Japanese yen and the US-Japan alliance to shift the pressure of expanding 4nm capacity in Chinese mainland to Japan to reduce the geopolitical risk.

05

Domestic News（Dec. 12）

Jingyi Automation Equipment successfully adapts to domestic most advanced 192-layer 3D NAND production line

The temperature control & exhaust gas treatment equipment of Beijing Jingyi Automation Equipment Co., Ltd. has been installed on the first 192-layer 3D NAND production line in China to achieve mass installation and the company has become the only domestic vendor to enter the node. The equipment can meet the requirements of wide temperature range of -70~120℃, with a tolerance of ±0.05℃ and high purity exhaust gas treatment. It has passed the rigorous one-year validation by top customers such as YMTC, redefined the target temperature control curve of the production line, ensuring the yield of high stack etching and film process.

The fact that Jingyi Automation Equipment entered the 192-layer 3D NAND production line proves that homemade semiconductor equipment has shifted from “usable” to “easy to use”. Although the temperature control & exhaust gas treatment equipment is a supporting process equipment, it directly determines the etching uniformity and film defect density. In the past, it was monopolized by Japanese and US manufacturers. The equipment of Jingyi Automation Equipment can run stably in the extreme temperature range from -70℃ to 120℃, with a tolerance of ±0.05℃, and defined customers’ temperature control curve, which means that the domestic vendor first has the voice in craftsman. Once the validation barrier has been formed, the replacement of imported products will be accelerated. Considering the exponential improvement in temperature control accuracy and exhaust gas cleanliness requirements of increasing 3D NAND layers, the pre-release data of Jingyi Automation Equipment will become an “Entrance Ticket” to tendering for subsequent 200+layer production expansion and will also open up space for homemade temperature control, vacuum and gas equipment.

06

Domestic News（Dec.12）

Gree Electric SiC chips successfully applied to new energy and industry fields

Gree Electric’s SiC power chips have leapfrogged from application in electrical appliances to new energy, industrial and special scenarios. In 2022, Zhuhai Gree Electronic Components Co., Ltd., established by Gree Electric, built the domestic leading 6/8-inch SiC wafer production line, covering an area of 200,000 square meters. The production line adopts fully automatic overhead traveling crane + grade 10,000 clean room, has a capacity of hundreds of thousands of wafers per year, and is certified to IATF16949 vehicle-grade system. The products mainly include 650V, 1200V Schottky diodes and MOSFET. The diode series have been certified to AEC-Q101 while some MOSFET platforms have been certified to vehicle grade systems, and they feature high pressure/temperature resistance and high efficiency.

With the higher percentage of new energy power generation and higher penetration rate of electric vehicles, the demand of SiC devices enters the explosive age. Gree Electric, relying on its huge cash flow and precision-making experience of home appliances, has reduced the yield curve to two third of the average period of the industry, and the yield of 1200V MOSFET has exceeded 85%. In addition, it plans to launch a 1700V platform in 2025 and make layouts in higher voltage scenarios like rail traffic, and flexible DC power grid. At the same time, the company developed the SiC module packaging line. With silver sintering, copper wire bonding and embedded packaging technology, it reduced the conduction loss by 8%, and the annual capacity of modules will be 3 million as scheduled. Gree Electric has signed long-term supply agreement with OEM vehicle suppliers and leading PV companies.

07

Domestic News（Dec. 9）

AMD unveils EPYC Embedded 2005 series processors

On December 9, AMD officially launched the EPYC Embedded 2005 series of processors, the first embedded x86 processor with Zen 5 architecture, to be used for 7×24 networking, storage and industrial edging equipment. All the three chip series adopt 40mm x 40mm GAG packaging, the TDP ranges 45 to 75W, with the highest 16 cores, 32-thread CUP, and 64 MB L3, and the main frequency is up to 4.5 GHz. This means that they support 28 lanes of PCIe 5.0 connectivity and DDR5-5600 Sideband ECC. Compared with Intel Xeon 6503P-B, the 12-core chips show a 35% improvement in baseline frequency, 28% improvement in acceleration frequency, 33% higher cache, power consumption down 50%, and package area down 2.4 folds, featuring significant cooling effect and saving space cost. The chips are designed for 10 years of running and 15 years of software maintenance. They are integrated with AMD Infinity Guard security suite, with enhanced RAS, supporting BMC, hot swap and wide temperature range of 0-105℃, which can meet the requirement of long-term deployments. The chip samples have been delivered, and they will be mass produced in Q1 2026. These chips will provide energy efficiency, highly scalable and clear lifecycle computing platforms for robots, cold storage, DPU, lightweight servers, and more, and will accelerate the embedded chip market to upgrade from DDR4 to DDR5. With IPC improved and energy-efficient ratios brought about by Zen 5 micro architecture, the EPYC Embedded 2005 series processors are expected to quickly replace traditional Xeon-D solutions in industrial edge computing, 5G base stations, smart Ethernet cards, and other scenarios, will become a key role of AMD to consolidate the share of the embedded data center.