01

Company Trend（May.06）

Vanguard International Semiconductor carefully evaluates the feasibility of a second 12-inch wafer fab

In May 2026, Fang Lue, Chairman of Vanguard International Semiconductor (VIS), stated at a shareholders’ meeting that the company is carefully evaluating the feasibility of constructing a second 12-inch wafer fab, but no final investment decision has been made. VIS currently operates one 12-inch fab (VSMC) in Singapore, primarily taking transferred orders from TSMC and producing mature-node chips of 28nm and above, serving clients in automotive electronics, power management, and display driver ICs.

Fang noted that global demand for 8-inch wafers remains weak, while competition in mature 12-inch nodes is intensifying. Mainland Chinese players such as SMIC and Hua Hong are actively expanding capacity, and combined with geopolitical uncertainties, the investment payback period carries significant risk. VIS’s revenue fell roughly 12% YoY in 2025, with gross margin pressured below 25%, and cash flow constraints making large-scale capital expenditures more cautious. The company emphasized that if a new fab proceeds, priority would be given to signing long-term capacity agreements (LTA) with strategic clients, while seeking government subsidies and joint-venture arrangements to share risks. The evaluation period is expected to continue through 2027.

Comments:The 12-inch mature-node segment (28nm and above) is currently caught in a vicious cycle of overcapacity, price competition, and shrinking margins, with aggressive expansion by SMIC and Hua Hong turning the field into a red-ocean market. If VIS follows with a new fab at this time, it would not only face the risk of clients being poached through lower-priced offers, but also further weaken its already fragile profitability due to depreciation burdens.

VIS has long relied on TSMC’s technology licenses and order transfers and lacks independent technological iteration capability. With advanced nodes below 7nm monopolized by TSMC and Samsung, and mature nodes facing competition from Mainland Chinese manufacturers, VIS’s market position is being squeezed from both ends. The LTAs and government subsidies mentioned by Fang essentially shift risks onto clients and taxpayers, but they do not address the fundamental lack of core competitiveness.

02

Company Trend（May.07）

Samsung Electronics launches 8nm eMRAM, advancing embedded memory to a new process node

Samsung Electronics announced the successful development of the industry’s first embedded magnetoresistive random access memory (eMRAM) based on an 8nm process, with customer sampling already underway. Built on Samsung’s second-generation eMRAM technology, the product is integrated on an 8nm logic process platform. Compared with the previous 14nm node, storage density has increased by approximately 2.3 times, write speed exceeds 20ns, endurance surpasses 10¹⁵ program/erase cycles, and data retention can exceed 10 years at temperatures of up to 85°C.

The launch of 8nm eMRAM marks the first time embedded non-volatile memory has entered the advanced FinFET era. Compared with conventional embedded flash (eFlash), eMRAM does not require additional high-voltage process modules and can scale together with logic circuits, significantly reducing chip area and manufacturing costs. Samsung stated that the product is primarily targeted at IoT devices, automotive electronics, and AI edge inference chips, addressing demand for low-power and highly reliable code storage and data logging. The company is currently working with multiple fabless design companies and expects mass production to begin in the first half of 2027.

Comments:Samsung’s launch of 8nm eMRAM represents a significant turning point in the technology roadmap for embedded memory. Conventional eFlash faces increasing scaling challenges below the 28nm node due to the limitations of floating-gate structures. By contrast, eMRAM, leveraging the physical properties of magnetic tunnel junctions (MTJs), is inherently better suited to advanced process scaling, helping resolve the structural bottleneck in which embedded memory lags behind logic scaling. The breakthrough is particularly significant for automotive electronics and edge AI applications. Automotive systems require highly durable memory for OTA updates and event logging, while edge AI devices rely on non-volatile memory to enable millisecond-level wake-up times and low standby power consumption.

However, the manufacturing cost of eMRAM remains higher than that of mature-node eFlash, and yield ramp-up will take time. More importantly, TSMC and Intel are also accelerating their deployment of eMRAM and ePCM technologies, meaning Samsung’s first-mover advantage window may last less than two years. In addition, the maturity of the design ecosystem—including EDA tool support and IP availability—will determine whether the technology can evolve from a promising prototype to large-scale commercialization.

03

Market Trend（May.08）

How next-generation AI chips are tackling the “Token Black Hole”

As large-scale AI models surpass the trillion-parameter scale, the cost of token generation during inference is increasingly becoming the industry’s “token black hole.” Current mainstream GPUs typically need to load full model weights when generating each token, making memory bandwidth the key constraint. For GPT-4-class models, memory usage during a single inference task can reach hundreds of gigabytes, while even HBM3e bandwidth remains insufficient to fully satisfy low-latency requirements. In 2026, chipmakers are pursuing three main approaches to address this challenge.

Computing-in-memory (CIM) architectures have emerged as a major breakthrough direction. Samsung Electronics and TSMC have already mass-produced SRAM-based CIM chips that embed multiply-accumulate units directly into memory arrays. In theory, this can improve energy efficiency by 10 to 100 times compared with conventional architectures, while enabling certain attention calculations to be performed directly within memory and reducing data movement. Sparse computing optimization is also advancing rapidly. Nvidia’s Rubin architecture supports dynamic structured sparsity, enabling zero-value computations to be skipped while maintaining model accuracy. This is expected to improve effective throughput by around 30%. In addition, dedicated inference processors such as Groq’s LPU adopt a Tensor Streaming Processor (TSP) architecture. By using deterministic execution to eliminate memory-access uncertainty, the chip reportedly achieves throughput of 800 tokens per second in Llama 3 inference workloads—approximately 10 times higher than conventional GPU-based solutions.

However, these approaches still face major ecosystem barriers. CIM chips require substantial software stack reconstruction, sparse computing introduces new constraints on model training, and dedicated inference chips remain limited by framework compatibility. Industry consensus suggests that the next two years will represent a critical window in which architectural divergence and convergence will coexist.

Comments:The “token black hole” essentially reflects the dual pressure of the memory wall and the compute wall, highlighting the structural transition of large-scale AI models from training-intensive workloads toward inference-intensive workloads. Current solutions show clear segmentation across use cases: computing-in-memory (CIM) architectures are well suited for low-power edge applications, but still face limitations in precision and flexibility; meanwhile, dedicated inference chips can deliver impressive performance on specific models, yet struggle to adapt to rapidly evolving model architectures. This fragmentation itself suggests that no single technological path is likely to dominate all scenarios.

A deeper challenge lies in hardware-software co-optimization. Without support at the framework layer—such as native optimization for sparse operators in PyTorch—architectural innovation risks remaining “theoretical performance” rather than practical performance gains. Nvidia’s core moat lies not only in hardware leadership, but also in the ability of the CUDA ecosystem to rapidly adapt to emerging architectures. As a result, challengers such as AMD and Intel will need to increase investment in software ecosystems such as ROCm and oneAPI; otherwise, hardware advantages may prove difficult to translate into real user experience improvements.

04

Company Trend（May.08）

AMD unveils Instinct MI430X GPU with FP64 performance exceeding 200 TFLOPS

In May 2026, AMD unveiled its new Instinct MI430X GPU at the High Performance Computing User Forum (HPCUF) held in Austin, Texas. Built on AMD’s next-generation CDNA architecture—expected to be CDNA 5—the MI430X is projected to deliver native FP64 performance exceeding 200 TFLOPS, reportedly more than six times that of Nvidia’s next-generation Rubin architecture. The product could become one of the most powerful GPUs ever developed for double-precision computing.

The MI430X is equipped with 432GB of HBM4 memory, delivering bandwidth of up to 19.6TB/s—more than double that of the previous MI350 series. This significantly alleviates memory bottlenecks in large-scale simulation and AI training workloads. Designed specifically for high-performance computing (HPC) applications, the chip supports FP64, FP8, and FP4 precision computing, targeting advanced scientific workloads including climate modeling, materials science, nuclear engineering, and computational fluid dynamics.

The MI430X has already been confirmed for deployment in the Discovery supercomputer at Oak Ridge National Laboratory, as well as in France’s Alice Recoque supercomputing project. The latter is expected to deliver more than 1 ExaFLOP of FP64 performance, positioning it among the most powerful HPC systems in Europe upon completion. Full technical specifications are expected to be officially disclosed during AMD’s Advancing AI event scheduled for July 22–23, 2026.

Comments:The release of the MI430X marks a targeted challenge by AMD to Nvidia in the high-performance computing (HPC) sector. However, claims of “crushing performance advantages” should be viewed rationally. The MI430X and Nvidia’s Rubin architecture are not designed for the same application scenarios: the former focuses primarily on HPC workloads, while the latter targets AI training and inference. Direct comparisons between the two therefore involve a mismatch in application context. In low-precision AI workloads, AMD still needs products such as the MI455X series to compete directly with Nvidia. In addition, software ecosystem capability remains one of AMD’s weaker areas, and the gap between ROCm and CUDA in developer adoption and ecosystem stickiness has yet to be fundamentally narrowed.

The launch of the MI430X breaks Nvidia’s long-standing dominance in the supercomputing segment and provides research institutions with an alternative option. As flagship projects such as Discovery and Alice Recoque move forward, AMD’s influence in national-level computing infrastructure is expected to continue rising. However, whether its hardware advantages can ultimately be converted into market share will still depend on ecosystem development and customer migration costs.

05

Company Trend（May.06）

Pengyue Technology to Build 12-Inch Wafer Fab in Wuhan with 28 Billion RMB, Focusing on Mature Process Nodes

In May 2026, Pengyue Technology announced the official groundbreaking of its 12-inch semiconductor wafer manufacturing project in Wuhan, Hubei Province. The project involves a total investment of approximately RMB 28bn and plans to build a 12-inch wafer production line with monthly capacity of 50,000 wafers. The fab will focus on mature process nodes ranging from 28nm to 55nm, serving applications including automotive electronics, industrial control, IoT, and display driver ICs. The project will be implemented in two phases, with the first phase expected to begin production by the end of 2027 and full-capacity operation targeted for 2028.

The launch of Pengyue Technology’s project represents another typical example of local governments betting on semiconductor manufacturing. With planned investment of RMB 28bn and monthly capacity of 50,000 wafers, the project is considered mid-sized within the mature-node segment. However, the market environment it faces is increasingly challenging. The 28nm–55nm segment is currently experiencing global overcapacity. Capacity utilization rates at major foundries such as SMIC, Hua Hong Semiconductor, and United Microelectronics Corporation have reportedly fallen to around 70%, while ongoing price competition continues to pressure margins. As a late entrant, Pengyue Technology lacks both technological differentiation and an established customer ecosystem. By the time the project reaches full production in 2028, it may face the most intense phase of competition in the mature-node market.

06

Company Trend（May.08）

Hwatsing Technology delivers ion implanter to leading domestic memory manufacturer

Chinese semiconductor equipment maker Hwatsing Technology recently announced the successful delivery of its self-developed ion implanter to a leading domestic memory manufacturer, marking a key breakthrough for China’s high-end front-end semiconductor equipment in memory fabrication. The system adopts medium-current ion implantation technology and is capable of supporting key process steps in 3D NAND and DRAM manufacturing, including source/drain doping and channel adjustment. The implantation energy range covers 2keV to 1MeV, while dose uniformity is controlled within ±0.5%, reaching the technical level of mainstream international equipment.

Ion implanters are among the highest-value core tools in semiconductor manufacturing and have long been dominated by US equipment suppliers such as Applied Materials and Axcelis, withdomestic substitution rates remaining below 5%. The latest delivery fills a key gap for domestic equipment in memory front-end processing. Following customer qualification, the product is expected to enter the volume procurement stage. The company stated that it will continue developing high-current and high-energy ion implanters to build a comprehensive implantation equipment portfolio covering both logic and memory applications. The development was also positively received by the capital market, with Hwatsing Technology’s share price rising more than 6% on the day of the announcement.

07

Domestic News（May.09）

China develops first dual-core atomic quantum “supercomputer,” with chip architecture emerging as key breakthrough

In May 2026, a research team led by Academician Pan Jianwei at the University of Science and Technology of China, together with Innovation Academy for Precision Measurement Science and Technology, announced the successful development of China’s first dual-core atomic quantum “supercomputer.” The system’s core innovation lies in its quantum processing chip architecture. Based on a neutral rubidium atom array approach, the system integrates two independent quantum processing cores, each containing more than 1,000 physical qubits. Using optical tweezer technology, the chip enables high-fidelity entanglement control between atoms at chip-scale level, while quantum state transfer fidelity between the two cores reaches 99.2%. Under quantum error-correction encoding, the system achieves more than 100 logical qubits and can stably execute quantum circuits exceeding 1,000 layers in depth.

The dual-core quantum chip adopts a modular partitioned architecture, dividing the qubit array into two independent modules. Inter-core communication is achieved through photon-mediated quantum teleportation, effectively reducing the impact of crosstalk noise on computational accuracy. The research team validated the system’s performance using random circuit sampling tasks, with results indicating computational speeds approximately 10¹⁵ times faster than simulations performed on classical supercomputers. The findings have been published in Nature Physics, marking a milestone breakthrough for China in scalable quantum computing chip architectures.